ROM and RAM Emulator for 8051

by Martin Clausen (mc AT rotgradpsi DOT de)

Hardware emulator for the 8051 family with 64K RAM and 64K ROM

Table of contents:


System Requirements

8086, some RAM, about 36kb harddiskspace, serial port, DOS or Windows (see this note)


emu [/h] [/info] [/slow] [/standby] [/w:FILENAME] [/com:COMPORT] [/irq:IRQ] [/read] [/data]

Parameter definition:

/infoshow full data transfer information
/slowforce slow mode, use if timing-code fails
/standbyloop program
/com:select comport
/irq:select irq for comport
/w:write to program memory, uses hex-file, extension will be ignored and set to .hex
/readforces /w: command to read data memory
/dataforces /w: command to work on data memory

If you use WinXX, you might create a link to emu on your desktop. Then you can insert there the command line. So you need only one click to send your program and one to close the window.

Otherwise you could also use the /standby option. Then you activate the window where emu is running and press simply a key. This especially useful during the development of a new program.

Emu does not cache the hex-file. It is read during the data transfer, therefor you can be sure that the latest version of the file is used.

If the green LED is on, the slave MCU is enabled. The MAX690 keeps the memory contents during power off. No resouces of the slave MCU are used. Wenn a SAB-C515 is used, it is possible to develop programs for the AT89-family easily by changing simply the port addresses. Remember that the address of the interrupt priority register at the 8051 is at the SAB-C515 the second interrupt enable register! Be careful also when you use the T2 of SAB-C515, compared to 8052 it is extended to a compare and capture unit. Do not ever write any 1's to bits that are not used by the basic 8051 architecture.

target MCU 87CXXP0 open drainP1P2P3
emulating MCU SAB-C515P4 quasi-bidirectionalP1P5P3

Principle of Operation

The system consists of two MCU, working on the same SRAM. The master controls the reset pin of the slave and establishes the connection to the PC. It has its own program memory, which is in the case of the 87C51 or 89C51 on chip. The 128K SRAM are for it divided into two banks of external data memory. They can be accessed when the slaves is reseted and the '157 forwards the control signals from the master to the SRAM.
When the master starts the slave, program and external data memory of the slave are mapped together via '00 and '157 on the SRAM. All resources of the slave are available to the user.
The MAX690 controls the circuit during power on and power down. It sets the SRAM in standby mode and provide power to maintain its content.
See the virtual walk through my 8051 development suite for a photo of the device including an image map.


Download of Program and Circuit

The part description in schematics is read as follows:
part type + value in exponential form + package description + subpart number in package
for example: C1040805,1 means Capacitor, 100nF, package SMD 0805, first subpart in package

Disclaimer: No warranty at all!
Copyright by Martin Clausen, Germany.
Contact the author: mc AT rotgradpsi DOT de