Digital Frequency Generator
by Martin Clausen (mc AT rotgradpsi DOT de)
Signal generator with DDS technology: 32 bit adder, 16 MHz, 16 bit DAC, AM & FM, MCU control, software adjustable via RS232
Table of contents:
- 16 Bit DAC, gives clear sine up to 2MHz with four times oversampling
- 2.5 MHz 9th order Butterworth filter
- 32 Bit adder, results in 0.0037 Hz tuning steps while running at 16MHz
- FM and AM:
- Software DDS in microcontroller
- Modulation with sine (or any other wavefrom), triangle and saw tooth
- 24 Bit adder, results in 0.0003 Hz tuning steps while running at 5.3 kHz for FM and 0.0005 Hz tuning steps while running at 8.9 kHz for AM
- Modulation with 16 Bit for FM, 12 Bit for AM
- 2 kHz 4th order Butterworth filter for AM signal
- Output voltage adjustable from 0 to +/- 12V
- Output offset adjustable from 0 to +/- 8V
- Standalone operation
- 16*2 LCD
- "Quasi logarithmic feeling" while tuning with rotary encoder
- Power On presets, recall power on presets button
- Remote control via RS232
- Comfortable adjustable via PC software, trimmer free design
- Communication protocol documentation
- Program is freeware for non-commercial use.
The circuit is controlled by a MCU. It is accompanied by a LCD, knobs, RS232 interface and an EEPROM. LCD and knobs allow a precise and user friendly frequency, amplitude and offset control.
The RS232 interface is necessary for adjustment and remote control of the frequency generator. The communication protocol allows direct control of the values of the shift register and DACs but also the transmission of frequency and voltage values in Hz and volt respectively. Direct control of the registers is faster, but the user have to calculate the values from the desired frequency and voltages on his own. The EEPROM stores power-up and calibration values.
Digital Frequency Generation
The digital part of the frequency generator consists of a shift register, an adder, a latch and a 1M bit EPROM. The shift register reduces the need of port pins at the MCU from 33 to 3. It also synchronises the data input from the MCU with the operation of the adder.
The adder output is feedback to itself via the latch. Therefore the value at the output of the latch is increased by the value in the shift register at every clock cycle. This value is also taken as an address for the EPROM. This EPROM contains a table, which allows to convert the value from the latch into the amplitude of the output signal. In principle any waveform can be stored and therefore generated.
The accuracy of the generated frequency is determed at low frequencies by the precision of the oscillator and at high frequencies by the jitter, which is caused by the discrete nature of adder and table.
The frequency and amplitude modulation is based on a DDS software in the microcontroller. Since the sinus is read from a 16K byte lookup table (LSB first) starting at &H01000, you can replace it by any other waveform.
Analog Processing of the Signal
The final output signal is formed through DAC, filter, multiplier and an amplifier. The digital output of the EPROM is converted to a analog signal by a high speed, high precision DAC. Its current output is converted to a voltage by a operational amplifier. To remove glitches and harmonics a Butterworth filter is employed.
The MCU shifts the amplitude value into the DAC. The output of the DAC is feed into the multiplier and allows the adjustment of the amplitude. The offset is adjusted by another DAC. Its output is converted to a bipolar output by a dual OP. In the final step the signal is amplified by a strong operational amplifier.
You can get most parts at Elpro, Germany
only sepcial parts are listed.
- 1 fg: AT89C55 or AT89C55WD, 33MHz; see also programming tips
- 1 fgsimple: AT89C51 or AT89S51; see also programming tips
- 1 74AC74
- 8 74AC283
- 4 74AC574
- 1 27C1002, 55ns max, Segor, Germany
- 1 fg: AD734, Segor, Germany
- 1 AD768, Farnell
- 1 AD811
- 2 fg: LT1013
- 1 LT1363
- 2 fg: LTC1257
- 49 10nF cer SMD
- 53 100nF cer SMD
- 4 1µF cer SMD
- 1 20 precision
- 1 24.9 precision
- 1 75 precision
- 1 499 precision
- 2 1k precision
- 1 fg: 32MHz quartz oscillator
- 1 12MHz quartz oscillator, my FG works also with 16MHz fine
- 1 fgsimple: crystal 11.0592MHz
- 1 rotary encoder Bourns ECW1JB24AC24 or 2 additional buttons (for encR and encL)
- 1 heatsink for AD811
- Do layout the pcb very careful to achieve full DAC performance:
- Do not use sockets for AD768, AD811, LT1363, all 74ACXXX and 74HC595
- Decouple with the recommend capacitor directly below ic
- Keep all wires as short as possible
- Keep 74ACXXX as far as possible from analogue circuits
- Connect analogue and digital GND only below the DAC
- Do not use conventional parts instead of SMD.
- Check voltages mentioned in schematics.
Those ideas lead to the following design:
- Beside his good performance, the AD734 causes excessive noise and might be replaced by a AD834. Up to now no other approach than a multiplier beside expensive GaAs attenuators is known to support frequencies above 100KHz. A -40db attenuator switch must be added for better performance.
- The performance of the filter should be increased, a sample and hold circuit maybe employed for deglitching.
- The AD768 should be replaced by a LT1668 for better SFDR and glitch performance.
- AC logic causes EMC problems and maybe replaced by a CPLD.
- EPROM speed is to low, there for it should be replaced by SRAM. Then the wave form is programmed by the µC and can also be altered. This can only be done when the AC logic is replaced by a CPLD.
- Jitter of the square signal output should be reduced by obtaining the signal from the filtered sinus signal via a comperator.
- EMC should be improved by a more professional PCB, enabling the use of modern SSOP packed chips and therefore the switch to 3.3V power supply.
Your help is welcome.
To allow you to customise you frequency generator fully to your needs, FGSimple is released. It is similar to FG, but does not support AM & FM, amplitude and offset control and employs only a 1*16 LCD to save costs. If you need only the digital output at low frequencies, you may also leave away EPROM, DAC, filter and output stage.
- DDS logic: XCR3256XL 256 macrocell CPLD, 64k*16 12ns SRAM, 40MHz oscillator
- DAC: LT1668
- PCB: SMD, four layer design
- fg.zip PC program for FG V1.06 with source code (for Power Basic 3.20 with Power Tools 2.00), ini-file
including MCU program V8
- fgsimple.zip PC program for FGSimple V1.04 with source code (for Power Basic 3.20 with Power Tools 2.00)
including MCU program V3 and version with LSB first to HC595
- fgmap.html memory map
- fgcom.html communication protocol documentation
- sin1mbit.zip lookup table for EPROM
other wave forms for 1M bit and 4M bit EPROMs on request
- fgpower.gif power supply
- fgmcu.gif MCU schematic
- fgsignalsyn.gif signal synthesis
- fgdac.gif dac
- fgfilter1.gif reconstruction filter for signal
- fgfilter2.gif reconstruction filter for AM
- fgoutput.gif output stage
The part description in schematics is read as follows:
part type + value in exponential form + package description + subpart number in package
for example: C1040805,1 means Capacitor, 100nF, package SMD 0805, first subpart in package
The exe and ini file are expected to be placed in the same folder!
|slower, cheap, low part count, PC controlled, AVR project||Jesper Hansen
Disclaimer: No warranty at all!
Copyright by Martin Clausen, Germany.
Contact the author: mc AT rotgradpsi DOT de