MiniDS
by Martin Clausen (mc AT rotgradpsi DOT de)
Mini Digital Storage Scope, one channel, low cost ADC, 8 Bit, 20MHz, 32K RAM, for connection via parallel port
Table of contents:
- Low cost, 20MHz, 8 Bit DAC
- 32K Bytes SRAM
- 20MHz, 200KHz and 2KHz sample rate via on board crystal oscillator and slower variable clock rates employing the PC
- Comfortable adjustable via PC software, single trimmer design
- DOS software (Martin Clausen) and Windows software (Martin Cízek)
- Lines for measurement signal voltages on screen
- Bilingual user interface in DOS version (German and English)
- Data can be streamed to hard disk.
- Helpfile included
- Communication protocol documentation
- Program is freeware for non-commercial use.
80386/Pentium, VGA, some RAM, about 100kB/250kB harddiskspace, parallel port DOS or Windows (see this note)
DOS version
Simply type minids and press enter. If you start the program for the first time or changed something, please enter minids /setup so you can check the configuration.
Windows version
Unpack the zip and start scope2.exe. Click on File and then Settings to adjust port address and frequency.
The input signal amplitude is reduced by resistors. The impedance of the input signal is then reduced by an operational amplifier. To allow positive and negative input signals, the level of the signal shifted to the middle of the range of the analog-digital-converter (ADC). This can be adjusted via a 5k trimmer. The input capacitance of the ADC is compensated through a capacitor in the level shifter. The input range of the circuit is about 13 volts peak to peak, but can be adjusted by chosing diverent input resistors.
The ADC is a flash converter. The PC selects a conversion frequency from the divider chain or generate one on its own. After the reset of the counter (74HC590), 32768 samples are taken by the circuit independently from the PC and stored in the SRAM. The data stream of 20MB per second could not be transferred through a parallel port. After the data acquisition is finished, the result is transferred in to the PC. The PC request the next byte by applying a clock cycle to the counter. Then the byte is transferred in two parts via the 74LS157 into the PC.
The 74LS14 is necessary to prevent latch-up and to reshape the signals. The 74HC390, 74HC251 and the quartz oscillator provide the clock signal for the counter. The 74HC251 is also used to stop data acquisition after the memory has been filled with data.
See Low-cost ADC for low cost design at lower sampling rates.
See PC osciloskop for a newer dual channel version of MiniDS with input stage, analogue trigger and windows software
- Semiconductors:
- 6 1N4001
- 1 74LS14
- 1 74LS157
- 1 74HC107
- 1 74HC251
- 2 74HC390
- 1 74HC590
- 1 32*8 SRAM, 15ns
- 1 TDA8703
- 1 LT1227
- 1 7805
- 1 78L05
- 1 78L08
- 1 79L08
- 1 40MHz quartz oscillator, my MiniDS works also with 50MHz fine
Capacitors:
- 1 22pF cer SMD
- 1 47pF cer SMD
- 3 22nF cer SMD
- 19 100nF cer
- 2 4.7µF
- 9 10µF
- 2 220µF
- 1 1000µF
Resistors:
- 1 22
- 2 1k SMD
- 1 1.8k SMD
- 1 5k pot
- 1 15k SMD
- 1 100k SMD
- 1 27k*8 / 9 pin sil array
Mechanic:
- 1 small heatsink for 7805
- 1 9V / 3,6VA
- 1 sub-D socket, 25 pin
- 1 cabel, sub-D plug-plug, 25 pin
- 1 case
- 1 pbc
- 1 some thin wire
- Do not use a socket for TDA8703 nor LT1227
- Place 22nF capacitors as close as possible to the TDA8703
- SelRange is connected to a input of a gate but its output is not connected, because its use is at the moment not supported by the minidspreamp. However the software is already capable of handling that signal. You might modify the minidspreamp on your own to make use of this signal.
The first three files are needed and expected to be placed in the same folder!
The part description in schematics is read as follows:
part type + value in exponential form + package description + subpart number in package
for example: C1040805,1 means Capacitor, 100nF, package SMD 0805, first subpart in package
| Description | Whom's work |
|---|
| PC osciloskop newer dual channel version of MiniDS with input stage, analogue trigger and windows software |
|
| DSO MK3, 2 channel DSO, employs expensive FIFO to get the same as this design, input stage applicable to MiniDS | David L. Jones
|
| BitScope, combined DSO and logic analyzer, employs PIC and CPLD to get the same as this design, uses slow RS232 connection instead of parallel port, input stage applicable to MiniDS | BitScope
|
Disclaimer: No warranty at all!
Copyright by Martin Clausen, Germany.
Contact the author: mc AT rotgradpsi DOT de
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